Texas Instruments /TM4C1231H6PGE /UDMA /STAT

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Interpret as STAT

31282724232019161512118743000000000000000000000000000000000000000000 (UDMA_STAT_MASTEN)UDMA_STAT_MASTEN0 (UDMA_STAT_STATE_IDLE)UDMA_STAT_STATE0UDMA_STAT_DMACHANS

UDMA_STAT_STATE=UDMA_STAT_STATE_IDLE

Description

DMA Status

Fields

UDMA_STAT_MASTEN

Master Enable Status

UDMA_STAT_STATE

Control State Machine Status

0 (UDMA_STAT_STATE_IDLE): Idle

1 (UDMA_STAT_STATE_RD_CTRL): Reading channel controller data

2 (UDMA_STAT_STATE_RD_SRCENDP): Reading source end pointer

3 (UDMA_STAT_STATE_RD_DSTENDP): Reading destination end pointer

4 (UDMA_STAT_STATE_RD_SRCDAT): Reading source data

5 (UDMA_STAT_STATE_WR_DSTDAT): Writing destination data

6 (UDMA_STAT_STATE_WAIT): Waiting for uDMA request to clear

7 (UDMA_STAT_STATE_WR_CTRL): Writing channel controller data

8 (UDMA_STAT_STATE_STALL): Stalled

9 (UDMA_STAT_STATE_DONE): Done

10 (UDMA_STAT_STATE_UNDEF): Undefined

UDMA_STAT_DMACHANS

Available uDMA Channels Minus 1

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